interfacing 7 segment display with 8086 processor

Statement: Program to interface 8086 microprocessor kit with Seven Segment Display and make any digit to Blink

Description:

In this program we interface 8086 microprocessor with Seven Segment Display and diaplay a digit.  To interface with Seven Segment Display,we must be familiar with 8255A PPI, which has three ports which can be used as I/O ports. The ports A, B and C are identified using addresses 19H, 1BH, and 1DH respectively and control register address is 1FH. We use Seven Segment Display structure using the following digit

	Digit	Hexadecimal	Decimal	Binary
8	0 1 2 3 4 5 6 7 8 9	C0 F9 A4 B0 99 92 82 F8 80 90	192 249 164 176 153 146 130 248 128 144	11000000 11111001 10100100 10110000 10011001 10010010 10000010 11111000 10000000 10010000

code: 

Source program:

 MOV AL,10000000B

 OUT PPI_C, AL

STR:   MOV AL, 10011001B

 OUT PPIA,AL

 MOV CX, FFFFH

DEL:    NOP

 NOP

 NOP

 LOOP DEL

 MOV AL, 11111111B

 OUT PPIA, AL

 MOV CX, FFFFH

DEL1:    NOP

 NOP

 NOP

 LOOP DEL1

 JMP  STR

 HLT

EXplanation of 8086 architecture

BUS INTERFACE UNIT:

• It provides a full 16 bit bidirectional data bus and 20 bit address bus.

• The bus interface unit is responsible for performing all external bus operations.

• Specifically it has the following functions:

• Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.

• The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.

• This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.

• These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle.

• After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.

• The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory.

• These intervals of no bus activity, which may occur between bus cycles are known as Idle state.

• If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.

• The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by  adding an appended 16 bit segment address and a 16 bit offset address.

• For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.

• The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.

EXECUTION UNIT

• The Execution unit is responsible for decoding and executing all instructions.

• The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands.

• During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.