interfacing 7 segment display with 8086 processor

Statement: Program to interface 8086 microprocessor kit with Seven Segment Display and make any digit to Blink

Description:

In this program we interface 8086 microprocessor with Seven Segment Display and diaplay a digit.  To interface with Seven Segment Display,we must be familiar with 8255A PPI, which has three ports which can be used as I/O ports. The ports A, B and C are identified using addresses 19H, 1BH, and 1DH respectively and control register address is 1FH. We use Seven Segment Display structure using the following digit

	Digit	Hexadecimal	Decimal	Binary
8	0 1 2 3 4 5 6 7 8 9	C0 F9 A4 B0 99 92 82 F8 80 90	192 249 164 176 153 146 130 248 128 144	11000000 11111001 10100100 10110000 10011001 10010010 10000010 11111000 10000000 10010000

code: 

Source program:

 MOV AL,10000000B

 OUT PPI_C, AL

STR:   MOV AL, 10011001B

 OUT PPIA,AL

 MOV CX, FFFFH

DEL:    NOP

 NOP

 NOP

 LOOP DEL

 MOV AL, 11111111B

 OUT PPIA, AL

 MOV CX, FFFFH

DEL1:    NOP

 NOP

 NOP

 LOOP DEL1

 JMP  STR

 HLT

EXplanation of 8086 architecture

BUS INTERFACE UNIT:

• It provides a full 16 bit bidirectional data bus and 20 bit address bus.

• The bus interface unit is responsible for performing all external bus operations.

• Specifically it has the following functions:

• Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.

• The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.

• This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.

• These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle.

• After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.

• The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory.

• These intervals of no bus activity, which may occur between bus cycles are known as Idle state.

• If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.

• The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by  adding an appended 16 bit segment address and a 16 bit offset address.

• For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.

• The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.

EXECUTION UNIT

• The Execution unit is responsible for decoding and executing all instructions.

• The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands.

• During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.

functional daigram of 8086

• 8086 has two blocks Bus Interfacing Unit(BIU) and Execution Unit(EU).

• The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue.

• EU executes instructions from the instruction system byte queue.

• Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.

• BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.

• EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,Flag register.

8086 pin diagram, and pin description

Figure shows the Pin diagram of 8086. The description follows it.

 

• The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package.
• The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode ) and other function in maximum mode configuration (multiprocessor mode ).
• The 8086 signals can be categorised in three groups.
• The first are the signal having common functions in minimum as well as maximum mode.
• The second are the signals which have special functions for minimum mode
• The third are the signals having special functions for maximum mode.
• The following signal descriptions are common for both modes.
• AD15-AD0 : These are the time multiplexed memory I/O address and data lines.  
• Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles.
• A19/S6,A18/S5,A17/S4,A16/S3 : These are the time multiplexed address and status lines.
• During T1 these are the most significant address lines for memory operations. 
• During I/O operations, these lines are low. 
• During memory or I/O operations, status information is available on those lines for T2,T3,Tw and T4.  
• The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.
• The S4 and S3 combinely indicate which segment register is presently being used for memory accesses as in below fig.
• These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is always low.
• The address bit are separated from the status bit using latches controlled by the ALE signal.

S4	S3	Indication
0 0 1 1 0 0 1	0 1 0 1 0 1 0	Alternate Data Stack Code or None Data Whole word Upper byte from or to even address Lower byte from or to even address

• BHE/S7 : The bus high enable is used to indicate the transfer of data over the higher order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledge cycle.

• RD – Read : This signal on low indicates the peripheral that the processor is performing memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge.

• READY : This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. the signal is active high.

• INTR-Interrupt Request : This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized.

• TEST : This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock.

• CLK- Clock Input : The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle.