General bus operation of 8086

• The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus.
• The main reason behind multiplexing address and data over the same pins is the maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP package.
• The bus can be demultiplexed using a few latches and transreceivers, when ever required.
• Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle.
• The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation.
• Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.

Maximum mode

• In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
• In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal using this status information .
• In the maximum mode, there may be more than one microprocessor in the system configuration.

Minimum mode

• In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.
• In this mode, all the control signals are given out by the microprocessor chip itself.
• There is a single microprocessor in the minimum mode system.